Solid state drive memory device comprising secure erase function
US9111621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jun 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device such as a solid state memory device have a dual-hardware, secure erase feature. A memory controller operating in a memory controller domain provides general memory management and interface operons. Upon receipt of a trigger signal which may be received from a secure supervisor circuit, a separate processor element that is configured to directly access the raw memory cells in the device bypasses the memory controller domain and executes a separately provided secure erase operating system whereby the raw cell data may be erased and rewritten with a predetermined data pattern and whereby the erase operation at the raw cell level may be verified and reported to the user by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.