Semiconductor memory systems using regression analysis and read methods thereof
US9111626B2 · kind B2 · utility
21Cited by
5References
32Claims
0Family size
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Key dates
| Filing date | Oct 24, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.