Method for fabricating semiconductor device having spacer elements
US9111906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | May 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.