LDMOS device and fabrication method

US9112025B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Beijing) Corporation · CN
• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Gangning Wang · Shanghai, CN
• Chih-Chung Tai · New Taipei, TW
• Guangli Yang · Nanhu, CN
• Jiwei He · Beijing, CN
• Xianyong Pu · Shanghai, CN

Key dates

• Filing date: Apr 8, 2014
• Grant date: Aug 18, 2015
• Expiry date: Apr 8, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

Various embodiments provide LDMOS devices and fabrication methods. An N-type buried isolation region is provided in a P-type substrate. A P-type epitaxial layer including a first region and a second region is formed over the P-type substrate. The first region is positioned above the N-type buried isolation region, and the second region surrounds the first region. An annular groove is formed in the second region to surround the first region and to expose a surface of the N-type buried isolation region. Isolation layers are formed on both sidewalls of the annular groove. An annular conductive plug is formed in the annular groove between the isolation layers. The annular conductive plug is in contact with the N-type buried isolation region at the bottom of the annular conductive plug. A gate structure of an LDMOS transistor is formed over the first region of the P-type epitaxial layer.