Circuit arrangement and method for generating a drive signal for a transistor
US9112497B2 · kind B2 · utility
1Cited by
17References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Sep 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.