Patent · US Active

Phase-locked loop start up circuit

US9112507B2 · kind B2 · utility

16Cited by

3References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Chien-Hung Chen · Taipei, TW
Mao-Hsuan Chou · Hengshan, TW
Tsung-Hsien Tsai · Pingzhen District, TW

Key dates

Filing date	Mar 9, 2010
Grant date	Aug 18, 2015
Priority date	—
Expiry date	May 11, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/101
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.