Cascoded semiconductor devices with gate bias circuit
US9116533B2 · kind B2 · utility
4Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2014 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Mar 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6875
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a cascode transistor circuit with a depletion mode transistor and a switching device. A gate bias circuit is connected between the gate of the depletion mode transistor and the low power line. The gate bias circuit is adapted to compensate the forward voltage of a diode function of the switching device. The depletion mode transistor and the gate bias circuit are formed as part of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.