Time reference systems for CPU-based and optionally FPGA-based subsystems
US9116561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | May 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0852
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A time reference system includes a master clock, generating a clock reference, interface logic and a CPU-based subsystem. The interface logic receives the clock reference and generates the clock, pulses, and timestamp signals. The CPU-based subsystem includes an internal counter, a CPU and a clock synthesizer, the CPU and receiving the pulses and timestamp signals. The clock synthesizer receives the clock signal and generates a CPU clock signal. Some examples include an FPGA-based subsystem having an FPGA-based card coupled to the interface logic for receipt of the clock, pulses and timestamp signals. In a method the timestamp value TO is generated by the CPU upon receipt of the timestamp signal. Upon receipt by the CPU of the next pulse signal, a timestamp counter baseline value TSCO is generated so the CPU internal counter is calibrated to the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.