Power consumption reduction method of swapping high load threads with low load threads on a candidate core of a multicore processor
US9116689B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jun 5, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing unit includes a processing unit including a plurality of processor cores; and a power consumption reduction device configured to reduce power consumption of the processing unit. The power consumption reduction device measures the loads on threads that are running in the plurality of cores; checks the number of high load threads which are threads in a high load state and the number of low load threads which are threads in a low load state for each core, on the basis of the measuring results; selects, when there exists a core having high load threads whose number is less than a preset threshold on the number of high load threads, the core as a candidate core; and replaces the high load threads existing in the candidate core with the low load threads existing in other cores when the total number of the low load threads in a core other than the candidate core is not less than the number of the high load threads in the candidate core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.