Use of cache to reduce memory bandwidth pressure with processing pipeline
US9116814B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Nov 27, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.