Memory controller
US9116825B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jan 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller is provided. The memory controller includes a memory interface and an encoding module. The memory interface is configured to couple to a memory chip. The encoding module is coupled to the memory interface and includes a shared memory and a parity generation module. The parity generation module is coupled to the shared memory. The parity generation module reads at least one basic vector from the shared memory, determines a dimension of the at least one basic vector, generates a generation matrix according to the at least one basic vector, converts a raw data into a codeword through the generation matrix, and stores the codeword into the memory chip through the memory interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.