Circuit for memory write data operation
US9117510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jan 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.