Memory cell with volatile and non-volatile storage
US9117521B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 14, 2012 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jun 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.