Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device
US9117658B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 23, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.