Semiconductor devices having balancing capacitor and methods of forming the same
US9117696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Nov 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.