Low power excess loop delay compensation technique for delta-sigma modulators
US9118342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Nov 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.