Clock phase alignment
US9118458B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2014 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Apr 24, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.