Instruction for shifting bits left with pulling ones into less significant bits
US9122475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2012 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.