Synchronizing a translation lookaside buffer with an extended paging table

US9122624B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Steven M. Bennett · Hillsboro, US
• Andrew V. Anderson · Forest Grove, US
• Gilbert Neiger · Portland, US
• Richard Uhlig · Hillsboro, US
• Dion Rodgers · Hillsboro, US
• Rajesh M. Sankaran · Portland, US
• Camron Rust · Hillsboro, US
• Sebastian Schoenberg · Hillsboro, US

Key dates

• Filing date: Oct 18, 2014
• Grant date: Sep 1, 2015
• Expiry date: Oct 18, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/7201
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.