Stacked multiple-input delay gates
US9122823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention disclose a method, program product, and a logic circuit structure for correcting early-mode timing violations in a digital circuit design. A portion of a digital circuit design is identified having an early-mode timing violation. A logic circuit is identified within the identified portion of a digital circuit design having the early-mode timing violation. At least one input of the identified logic circuit is identified as having the early-mode timing violation. At least one transistor is added to the identified logic circuit, wherein the input of the added at least one transistor is coupled to the identified at least one input of the identified logic circuit, and wherein the addition of the at least one transistor delays the signal received at the identified at least one input to eliminate the early-mode timing violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.