Low latency synchronization scheme for mesochronous DDR system
US9123408B2 · kind B2 · utility
6Cited by
7References
25Claims
0Family size
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Key dates
| Filing date | May 24, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.