Adaptive data-retention-voltage regulating system for SRAM
US9123436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) is revealed. The system includes a power supply unit, a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of SRAM, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal. The DVR monitor cell consists of a DRV monitor circuit mounted with a plurality of memory cells, a reset signal generating circuit for resetting the DRV monitor circuit, and an adaptive variation control circuit that generates noise bias according to leakage current to adjust reaction speed of the DRV monitor circuit correspondingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.