Configurable delay circuit and method of clock buffering
US9123438B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.