Method and apparatus for memory speed characterization
US9123446B1 · kind B1 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Apr 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.