Semiconductor device
US9123554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Dec 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention is to improve noise immunity to the power supply and ground of a wiring board and a second semiconductor chip in an interior of a semiconductor device. A first semiconductor chip is mounted over a wiring board, and a second semiconductor chip is mounted in a central part located over the first semiconductor chip. Bottom surface electrodes of power and ground systems in the second semiconductor chip are led to their corresponding external coupling electrodes formed in the central part of the wiring board though chip through vias formed in the central part of the first semiconductor chip. The power and ground system bottom surface electrodes, the through vias and the external coupling electrodes are respectively arranged discretely from each other between the power and ground systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.