Semiconductor structure and manufacturing method thereof
US9123612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate, an imaging pixel array disposed on a first region of the substrate, a first isolation disposed in the first region, a periphery circuitry disposed on a second region of the substrate, and a second isolation disposed in the second region. The imaging pixel array has a plurality of imaging pixels configured to capture image data. The periphery circuitry has a transistor configured to receive and process the image data. The first isolation has a first depth and a first protrusion projected from a surface of the substrate. The second isolation has a second depth and a second protrusion projected from the surface of the substrate. The first protrusion has a substantially same height as the second protrusion. The first depth is different from the second depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.