Methods of forming secured metal gate antifuse structures
US9123724B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.