Directional coupler integrated by CMOS process
US9123982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2012 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Jan 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P5/187
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A directional coupler is disclosed integrated on a single chip and an integrated circuit based on a standard CMOS process and relates to a field of radio frequency communication. In exemplary implementations, by using a standard CMOS process technology, the directional coupler integrated by a CMOS process is formed by a coil wound by a upper layer of metal lines, a coil wound by a lower layer of metal lines, two tuning capacitor array, and a matching resistor. Two terminals of the coil are a direct terminal and an input terminal; two terminals of the coil are a coupled terminal and an isolation terminal; the terminals of the coils and are intersected at 90°; the coil is wound by an upper metal layer and the coil is wound by a lower metal layer. Further, the insertion loss is low and the isolation degree is large.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.