Digital-to-analog converter with correction for parasitic routing resistance
US9124282B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2014 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Mar 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of a digital-to-analog converter circuit includes a resistor network connected to an output node, a switch network having a first plurality of switches connecting the resistor network to a first circuit node and a second plurality of switches connecting the resistor network to a second circuit node, a voltage reference to supply a reference voltage to the first circuit node, and a current generator connected to the first circuit node and the second circuit node, to generate a compensation current, draw the compensation current from the first circuit node, and supply the compensation current to the second circuit node. The current generator can generate the compensation current as a function of a current or a voltage of a component of the voltage reference or as a function of an analog output voltage produced at the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.