Scrambler with built in test capabilities for unary DAC
US9124287B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs. Each of the N unique scrambling stages is operable to pass signals at the inputs to the outputs in either an unscrambled or scrambled state under control of a control bit provided by an N-bit entropy signal. When an N+1 bit input signal is applied to the scrambler inputs and the N-bit entropy signal is randomized the analog output signal from the DAC has improved linearity compar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.