Processor that transitions to an idle mode when no task is scheduled to execute and further enters a quiescent doze mode or a wait mode depending on the value of a reference counter
US9128703B1 · kind B1 · utility
11Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2008 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Oct 8, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quiescent doze mode permits significant reductions in power consumption and dissipation by electronic devices while idle without producing adverse latencies to users. Device drivers communicate predictions as to future use of their coupled devices with a kernel. The kernel may then enter a quiescent doze mode comprising gating clocks on the processor and peripherals, disabling interrupts, and executing a wait for interrupt. Dynamically increasing timer interrupt intervals to significant fractions or multiples of a second further increases the percentage of time the device remains in quiescent doze mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.