Power saving techniques that use a lower bound on bit errors
US9128710B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 24, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Oct 22, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.