Processor with memory race recorder to record thread interleavings in multi-threaded software

US9128781B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Tim Kranich · Braunschweig, DE
• Gilles A. Pokam · Fremont, US
• Justin E. Gottschlich · Santa Clara, US
• Klaus Danne · Braunschweig, DE
• Rolf Kassa · Amberg, DE
• Shiliang Hu · Los Altos, US
• Cristiano L. Pereira · Sunnyvale, US

Key dates

• Filing date: Dec 28, 2012
• Grant date: Sep 8, 2015
• Expiry date: Feb 13, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/3409
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.