Patent · US Active

Interrupt handling systems and methods for PCIE bridges with multiple buses

US9128920B2 · kind B2 · utility

1Cited by

37References

23Claims

0Family size

Assignee

Marvell World Trade Ltd. · BB

Inventors

Xiongzhi Ning · Karlsruhe, DE
Steffen Dolling · Ditzingen, DE
Markus Althoff · Achern, DE

Key dates

Filing date	Nov 29, 2012
Grant date	Sep 8, 2015
Priority date	—
Expiry date	Dec 2, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2213/0026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.