Semiconductor device with chip having a different number of front surface electrodes and back surface electrodes
US9129828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Sep 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.