Three-dimensional semiconductor memory devices having double cross point array and methods of fabricating the same
US9129830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2012 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Jan 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include first, second and third conductive lines disposed at different vertical levels to define two intersections, and two memory cells disposed at the two intersections, respectively. The first and second conductive lines may extend parallel to each other, and the third conductive line may extend to cross the first and second conductive lines. The first and second conductive lines can be alternatingly arranged along the length of third conductive line in vertical sectional view, and the third conductive line may be spaced vertically apart from the first and second conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.