Mask level reduction for MOFET
US9129868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2012 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Aug 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.