Bonding pad arrangment design for multi-die semiconductor package structure
US9129962B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2014 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor package structure. The semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die comprises a plurality of third pads with the first pad area and a plurality of fourth pads with the second pad area alternately arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the fourth pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.