Electronic devices

US9130179B2 · kind B2 · utility

Assignee

• PLASTIC LOGIC LIMITED · GB

Inventors

• Martin Jackson · Stowmarket, GB
• Catherine Ramsdale · Cambridge, GB
• Jerome Joimel · Westfield, GB

Key dates

• Filing date: Nov 25, 2011
• Grant date: Sep 8, 2015
• Expiry date: Apr 29, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10K10/466

Abstract

A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.