Data holding circuit and semiconductor integrated circuit device
US9130555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit including: an input stage that includes a first input unit into which input data is input and a pair of first output units and is driven by a first power-supply voltage; a pair of first gate elements that includes first transistors, and is driven by a clock that includes a second power-supply voltage that is lower than the first power-supply voltage; a first latch circuit that includes a pair of second input units, and is driven by the first power-supply voltage; a pair of second gate elements that includes second transistors, and is driven by an inverted clock of the clock; and a second latch circuit that includes a pair of third input units, and a third output unit that outputs one of a pair of pieces of data, and is driven by the first power-supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.