Controllable polarity FET based arithmetic and differential logic
US9130568B2 · kind B2 · utility
1Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.