Patent · US Active

Redundant delay digital-to-time converter

US9130588B2 · kind B2 · utility

2Cited by

2References

5Claims

0Family size

Assignee

Intel Mobile Communications GmbH · DE

Inventors

Stephan Henzler · Munich, DE
Markus Schimper · Erding, DE
Paolo Madoglio · Beaverton, US
Stefano Pellerano · Beaverton, US
Kailash Chandrashekar · Portland, US

Key dates

Filing date	Mar 15, 2013
Grant date	Sep 8, 2015
Priority date	—
Expiry date	Aug 5, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/08
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.