Time keeping in unknown and unstable clock architecture
US9134751B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0655
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention may provide a system with a fixed clock to provide a fixed clock signal, and a variable clock to provide a variable clock signal. The system may also include a chipset with a chipset time stamp counter (TSC) based on the fixed clock signal. A processor may include a fast counter that may be based on the variable clock signal and generate a fast count value. A slow counter may download a time stamp value based on the chipset TSC at wakeup. The slow counter may be based on the fixed clock signal and may generate a slow count value. A central TSC may combine the fast count and slow count value to generate a central TSC value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.