Power-gating in a multi-core system without operating system intervention
US9134787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jan 6, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.