Run-time code parallelization with monitoring of repetitive instruction sequences during branch mis-prediction
US9135015B1 · kind B1 · utility
13Cited by
34References
30Claims
0Family size
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Key dates
| Filing date | Dec 25, 2014 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Dec 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, in a processor that executes instructions of program code, monitoring the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions. In response to detecting a branch mis-prediction in the monitored instructions, the specification is corrected so as to compensate for the branch mis-prediction. Execution of the repetitive sequence is parallelized based on the corrected specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.