Data processing device and data processing method
US9135108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present technique relates to a data processing device and a data processing method that enable resistance to error of data to be improved.In the case in which an LDPC code having a code length of 16200 bits and an encoding rate of 8/15 is mapped to 16 signal points, if (#i+1)-th bits from most significant bits of sign bits of 4×2 bits and symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, respectively, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y0, y4, y3, y1, y2, y5, y6, and y7, respectively. The present technique can be applied to a transmission system or the like transmitting an LDPC code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.