Multi-threaded memory management
US9135183B2 · kind B2 · utility
2Cited by
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27Claims
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Key dates
| Filing date | Aug 23, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jan 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.