Method of designing power supply network
US9135390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2014 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/0005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.