Non-planar field effect transistor having a semiconductor fin and method for manufacturing
US9136356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2014 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.