Power supply selector and method for minimizing an inrush current in a power supply selector
US9136698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | May 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/001
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for minimizing an inrush current in a power supply selector and a power supply selector system is provided. The power supply selector includes a plurality of power input nodes, a power output node, a first transistor and a second transistor. Each of the power input nodes may be coupled to a first switch having a first on-resistance and to a second switch having a second on-resistance. The second on-resistance is greater than the first on-resistance. The first switch and the second switch are preferably coupled in parallel. The power supply selector may be configured to couple a selected one of the power input nodes to the source of the first transistor and to the gate of the second transistor so as to sense a sense voltage at the selected power input node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.